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US 9,431,079 B1Granted
Systems and methods of memory and memory operation involving input latching, self-timing and/or other features
AssigneeGSI Technology, Inc.
InventorsLeelean Shu, Yoshi Sato, Hsin You S. Lee
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Abstract
Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from control circuitry.
Claims12
A semiconductor memory device comprising:
- a self-timed pulse generator configured to receive a clock signal and generate a self-timed pulse having a first edge corresponding to a rising edge of the clock signal and a second edge;
- first input latch circuitry configured to receive the self-timed pulse and a memory operation command and generate an internal memory operation command set to a latched state corresponding to the first edge of the self-timed pulse;
- read/write control circuitry configured to receive the self-timed pulse and internal memory operation signal and perform a read operation and a write operation for at least one memory address, the read operation being performed corresponding to one of the first edge and second edge of the self-timed pulse, and the write operation being performed corresponding to one of the first edge and second edge of the self-timed pulse, wherein the read/write control circuitry is configured to control row and column addresses of the at least one memory address using section address data that is separate from a read pulse during the read operation;
- and
- second input latch circuitry configured to receive the self-timed pulse and a memory address and generate an internal address signal set to a latched state corresponding to the first edge of the self-timed pulse, wherein the section address data is used to synchronize memory operations associated with the row and column addresses propagating into and out of the memory;
- wherein the self-timed pulse generator is further configured to adjust a width of the self-timed pulse to ensure the completion of the read operation;
- and
- wherein the read/write control circuitry is configured to align write address timing and data timing associated with the write operation via:
- for section addressing operations, multiplexing a read address and a write address using the read pulse and a write pulse;
- for row and column addressing operations, multiplexing the read address and the write address using only the write pulse;
- and
- operating a plurality of registers in a write address path and at least one register in a data path, wherein the registers in the write path and the at least one register in the data path align the write address timing and the data timing associated with the write operation.
9 more elements
A method of memory operation, the method comprising:
- processing a clock signal;
- generating, with a self-timed pulse generator, a self-timed pulse having a first edge corresponding to a rising edge of the clock signal and a second edge;
- processing, via a first input latch circuit, the self-timed pulse and a memory operation command;
- generating, via the first input latch circuit, an internal memory operation command set to a latched state corresponding to the first edge of the self-timed pulse;
- processing, via a read and write control circuit, the self-timed pulse and internal memory operation signal;
- performing, via the read and write control circuit, a read operation and a write operation for at least one memory address, the read operation being performed corresponding to one of the first edge and second edge of the self-timed pulse, and the write operation being performed corresponding to one of the first edge and second edge of the self-timed pulse, wherein, during the read operation, row and column addresses of the at least one memory address are controlled using section address data that is separate from a read pulse;
- processing, via a second input latch circuit, the self-timed pulse and a memory address, wherein the section address data is used to synchronize memory operations associated with the row and column addresses propagating into and out of the memory;
- generating, via the second input latch circuit, an internal address signal set to a latched state corresponding to the first edge of the self-timed pulse;
- and
- adjusting, with the self-timed pulse generator, a width of the self-timed pulse to ensure the completion of the read operation;
- wherein write address timing and data timing associated with the write operation are aligned via:
- for section addressing operations, multiplexing a read address and a write address using the read pulse and a write pulse;
- for row and column addressing operations, multiplexing the read address and the write address using only the write pulse;
- and
- operating a plurality of registers in a write address path and at least one register in a data path, wherein the registers in the write path and the at least one register in the data path align the write address timing and the data timing associated with the write operation.
12 more elements
Dependencies are inferred from the claim text.