Low power memory device
AssigneeChih-Cheng Hsiao
InventorChih-Cheng Hsiao
Life of this patent
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Abstract
A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured.
Claims14
A memory device comprising:
- a memory cell unit including a plurality of memory cell groups, each of said memory cell groups including at least one memory cell for storing data therein;
- a bit line unit including a plurality of first bit lines, each of which is coupled to said at least one memory cell of a respective one of said memory cell groups, and a second bit line for transmitting to-be-read data;
- and
- a buffering unit including a plurality of tri-state buffers, each of said tri-state buffers having an input terminal coupled to a respective one of said first bit lines, and an output terminal coupled to said second bit line;
- wherein said plurality of first bit lines is not directly connected to said second bit line.
Dependencies are inferred from the claim text.