Dynamic random access memory (DRAM) with low variation transistor peripheral circuits

A dynamic random access memory (DRAM), comprising:

• at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor;
• a body bias control circuit configured to generate a body bias voltage from a bias supply voltage, the body bias voltage being different from a power supply voltage of the DRAM;
• and
• peripheral circuits formed in the same substrate as the at least one DRAM cell array, the peripheral circuits having at least one deeply depleted channel (DDC) transistor having a body coupled to receive the body bias voltage, the DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region, the screening region having a first dopant concentration that is no less than 1×1018 dopant atoms/cm3 and that is different from a second dopant concentration of a substrate portion or well containing the DDC transistor;
• wherein:
• the peripheral circuits comprise a digital delay line circuit including at least a fine delay circuit having a plurality of delay stages arranged in series, each delay stage including DDC transistors;
• and
• the body bias control circuit is a delay control circuit configured to apply different body biases to the DDC transistors of the delay stages in response to a delay set value.