Stacked memory having same timing domain read data and redundancy
AssigneeRambus Inc.
InventorsFrederick A. Ware, Paul D. Franzon
Life of this patent
Estimating the term…
Abstract
A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.
Claims20
A memory comprising:
- a first integrated circuit (IC) chip having first storage;
- a second IC chip stacked with the first IC chip and having second storage;
- a third IC chip stacked with the first and second IC chips;
- and
- logic to aggregate first read data accessed from one or both of the first and second IC chips with second read data accessed from the third IC chip, the logic to re-time the aggregated first and second read data into the same timing domain and to transfer the re-timed read data to a memory controller.
A method of operation in a memory, the memory having first, second and third integrated circuit (IC) chips disposed in a stacked relationship, the method comprising:
- accessing first read data from at least one of a first IC chip and a second IC chip;
- accessing second read data from a third IC chip;
- aggregating the first and second read data in one of the first, second or third IC chips;
- re-timing the aggregated first and second read data into the same timing domain;
- and
- transferring the re-timed read data to a memory controller.
A memory module comprising:
- a substrate having an external databus for coupling to a memory controller;
- and
- a plurality of stacked memories disposed on the substrate, each of the stacked memories including
- a first integrated circuit (IC) chip having first storage,
- a second IC chip stacked with the first IC chip and having second storage,
- a third IC chip stacked with the first and second IC chips, and
- logic to aggregate first read data accessed from one or both of the first and second IC chips with second read data accessed from the third IC chip, the logic to re-time the aggregated first and second read data into the same timing domain and to transfer the re-timed read data along the external databus to the memory controller.
Dependencies are inferred from the claim text.