Execution model for heterogeneous computing
AssigneeQUALCOMM Incorporated
InventorsAlexei V. Bourd, William F. Torzewski
Life of this patent
Estimating the term…
Abstract
The techniques are generally related to implementing a pipeline topology of a data processing algorithm on a graphics processing unit (GPU). A developer may define the pipeline topology in a platform-independent manner. A processor may receive an indication of the pipeline topology and generate instructions that define the platform-dependent manner in which the pipeline topology is to be implemented on the GPU.
Claims20
A method for heterogeneous computing, the method comprising:
- receiving, with a processor, a pipeline topology of an execution model that defines a data processing algorithm in a platform-independent manner;
- generating, with the processor, instructions that indicate a platform-dependent manner in which the pipeline topology of the execution model is to be implemented on a graphics processing unit (GPU), wherein the platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU is based on a platform of the GPU, wherein the pipeline topology identifies producer kernels that produce data that is to be consumed by consumer kernels, wherein the instructions are based on an amplification factor, and wherein a maximum amount of data that is to be produced by the producer kernels is based on the amplification factor and an amount of data that the producer kernels will receive;
- and
- transmitting, with the processor, the instructions to the GPU.
An apparatus comprising:
- a graphics processing unit (GPU);
- and
- a processor configured to:
- receive an indication of a pipeline topology of an execution model that defines a data processing algorithm in a platform-independent manner;
- generate instructions that indicate a platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU, wherein the platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU is based on a platform of the GPU, wherein the pipeline topology identifies producer kernels that produce data that is to be consumed by consumer kernels, wherein the instructions are based on an amplification factor, wherein a maximum amount of data that is to be produced by the producer kernels is based on the amplification factor and an amount of data that the producer kernels will receive;
- and
- transmit the instructions to the GPU.
A non-transitory computer-readable storage medium having instructions stored thereon that when executed by one or more processors cause the one or more processors to:
- receive a pipeline topology of an execution model that defines a data processing algorithm in a platform-independent manner;
- generate instructions that indicate a platform-dependent manner in which the pipeline topology of the execution model is to be implemented on a graphics processing unit (GPU), wherein the platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU is based on a platform of the GPU, wherein the pipeline topology identifies producer kernels that produce data that is to be consumed by consumer kernels, and wherein the instructions are based on an amplification factor, and wherein a maximum amount of data that is to be produced by the producer kernels is based on the amplification factor and an amount of data that the producer kernels will receive;
- and
- transmit the instructions to the GPU.
An apparatus comprising:
- a graphics processing unit (GPU);
- and
- a processor comprising:
- means for receiving a pipeline topology of an execution model that defines a data processing algorithm in a platform-independent manner;
- means for generating instructions that indicate a platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU, wherein the platform-dependent manner in which the pipeline topology of the execution model is to be implemented on the GPU is based on a platform of the GPU, wherein the pipeline topology identifies producer kernels that produce data that is to be consumed by consumer kernels, wherein the instructions are based on an amplification factor, and wherein a maximum amount of data that is to be produced by the producer kernels is based on the amplification factor and an amount of data that the producer kernels will receive;
- and
- means for transmitting the instructions to the GPU.
Dependencies are inferred from the claim text.