Processor related noise encryptor

A method comprising:

• selecting a plurality of frequencies for a first noise output, the plurality of frequencies within a range of frequencies of a second noise output, the second noise output produced by one or more first voltage regulating modules providing power to a processor;
• selecting an amplitude for each frequency of the plurality of frequencies of the first noise output;
• producing the first noise output based on one or both of the plurality of frequencies and the amplitude for each frequency, wherein the first noise output combines with the second noise output to produce a third noise output such that a coherence between the third noise output and operations of the processor is below a threshold;
• and
• detecting the third noise output using a transducer.

A system comprising:

• a processor;
• one or more first voltage regulating modules that provide power to the processor;
• one or more second voltage regulating modules that provide scrambling noise;
• a frequency selection module that selects a plurality of frequencies for a first noise output, the plurality of frequencies within a range of frequencies of a second noise output, the second noise output produced by the one or more first voltage regulating modules;
• an amplitude selection module that selects an amplitude for each frequency of the plurality of frequencies of the first noise output;
• a noise scrambling module that produces the first noise output based on one or both of the frequency selection module and the amplitude selection module, wherein the first noise output combines with the second noise output to produce a third noise output such that a coherence between the third noise output and operations of the processor is below a threshold;
• and
• a noise detection module comprising a transducer, wherein the transducer detects the third noise output;
• wherein said modules comprise one or more of a hardware circuit, a programmable logic device, and code stored on one or more computer readable storage devices, wherein when the code is stored on one or more computer readable storage devices, the code is executable by the processor.