Failure analysis and inline defect characterization
AssigneeSynopsys, Inc.
InventorAnkush Oberai
Life of this patent
Estimating the term…
Abstract
Defect characterization and failure analysis are useful tools for analyzing and improving fabrication for semiconductor chips. By using a layout and a netlist in combination with images of semiconductors, defects can be identified and analyzed. Electrical simulation can be performed on the netlist, based on the presence of the defect that was detected. Layout geometries where the defect was detected can be binned, and a search can be performed of the remainder of the layout for similar groupings of layout geometries. Various representations of the semiconductor can be cross-mapped, including layout, schematic, and netlist. The presence of certain defects can be correlated to yield, to performance, and to other characteristics.
Claims27
A computer implemented method for performing semiconductor failure analysis comprising:
- having a set of rules wherein each rule of the set of rules describes a design rule check for a semiconductor layout;
- selecting a rule from the set of rules to apply to the semiconductor layout wherein the rule describes a two-dimensional Boolean operation on shapes where the rule further describes shapes of one or more layers and shapes of potential defects derived from defect scanning tools or yield managements systems, wherein the Boolean operation on shapes further includes shapes of electrical traces identified from electrical analysis of a netlist representing circuitry in the semiconductor layout;
- identifying a portion of the semiconductor layout by searching through the semiconductor layout for a match to the rule which was selected;
- and
- displaying the portion of the semiconductor layout.
A computer program product embodied in a non-transitory computer readable medium, when executed by a processor, causes the processor to perform defect characterization, the computer program product comprising instructions that when executed cause the processor to:
- inspect images of a semiconductor chip comprising a semiconductor circuit during fabrication to look for an anomaly in the images by comparing the images to known good images, resulting in detecting a defect in the images;
- perform electrical analysis of a netlist, for the semiconductor circuit, with the defect which was detected to perform electrical simulation of the netlist, for the semiconductor circuit with the defect wherein the electrical simulation includes a range of resistive shorts for the defect;
- and
- rank the defect based on impact to operation of the semiconductor circuit, based on the range of resistive shorts.
A computer-implemented method of defect characterization comprising:
- inspecting images of a semiconductor chip which comprises a semiconductor circuit during fabrication to look for an anomaly in the images by comparing the images to known good images, resulting in detecting a defect in the images wherein the detecting includes detecting where the defect is larger than a critical dimension in one of the images of the semiconductor chip;
- using a schematic for the semiconductor circuit and cross mapping between the schematic and a netlist or a layout for the semiconductor circuit;
- and
- performing, using one or more processors, electrical analysis of the netlist with the defect which was detected.
A computer system for defect characterization comprising:
- a memory for storing instructions;
- one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
- inspect images of a semiconductor chip comprising a semiconductor circuit during fabrication to look for an anomaly in the images by comparing the images to known good images, resulting in detecting a defect in one of the images wherein detection includes detecting where the defect is larger than a critical dimension in one of the images of the semiconductor chip;
- use a schematic for the semiconductor circuit and cross map between the schematic and a netlist or a layout for the semiconductor circuit;
- and
- perform electrical analysis of the netlist with the defect which was detected.
Dependencies are inferred from the claim text.