Back to results
US 9,430,601 B2Granted
Method and apparatus for automatic relative placement generation for clock trees
AssigneeSynopsys, Inc.
InventorAnand Arunachalam
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
Claims24
A system for circuit design, comprising:
- an EDA system performing a transformation of a hardware description language circuit representation into a physical circuit representation with a clock tree of clock network flip-flops,
- wherein the EDA system complies with a plurality of sets of rules created at different times, and
- wherein the EDA system adds clock network buffer circuitry, including an instance with the clock network flip-flops having integrated clock gating,
- wherein the system automatically creates the clock network flip-flops after coarse placement and before clock tree synthesis.
1 more element
A tangible non-transitory computer readable medium with computer readable instructions executable by a computer system, comprising:
- instructions executable by the computer system to transform a hardware description language circuit representation into a physical circuit representation with a clock tree of clock network flip-flops,
- wherein the instructions comply with a plurality of sets of rules created at different times, and
- wherein the instructions add clock network buffer circuitry, including an instance with the clock network flip-flops having integrated clock gating,
- wherein the computer system automatically creates the clock network flip-flops after coarse placement and before clock tree synthesis.
1 more element
Dependencies are inferred from the claim text.