Dual mode logic circuits

A method for designing a dual-mode logic circuit, wherein said logic circuit is selectably operational in static and dynamic modes, said method comprising:

• providing a basis library comprising a DML logic gate inverter and a plurality of dual-mode logic (DML) bicells, each of said DML bicells comprising:
• i) a type-A DML logic gate including a clock input and being independently selectable for static or dynamic mode;
• and
• ii) a type-B DML logic gate including an inverted clock input and being independently selectable for static or dynamic mode;
• forming a pseudo-static library from said basis library by:
• i) modifying each bicell of said basis library by removing respective clock and inverted clock inputs into said bicells;
• and
• ii) specifying respective values of at least one dynamic timing parameter for said DML inverter and for each of said modified pseudo-static library bicells;
• forming a dynamic library from said basis library by specifying respective values of a plurality of dynamic timing parameters for said DML inverter and for each bicell of said basis library;
• defining a logic behavior of a required logic circuit;
• obtaining an initial logic circuit design by synthesis of said pseudo-static library and said defined logic behavior;
• and
• forming a dynamic circuit design by replacing modified pseudo-static library bicells in said initial logic circuit design with corresponding bicells from said dynamic library,
• wherein the synthesis of said pseudo-static library and said defined logic behavior is implemented by an electronic design automation system.