System and method for conserving memory power using dynamic memory I/O resizing
AssigneeQUALCOMM Incorporated
InventorsHaw-Jing Lo, Dexter Chun
Life of this patent
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Abstract
Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.
Claims32
A method for conserving power consumption in a memory system, the method comprising:
- receiving a memory request from a memory client residing on a system on chip (SoC) for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC via a memory bus comprising a single memory channel;
- determining that the memory request from the memory client corresponds to a performance use case for using less than a full width of the memory bus;
- and
- conserving memory power consumption for the memory request corresponding to the performance use case by dynamically resizing the memory bus to less than the full width, wherein dynamically resizing the memory bus to less than the full width comprises:
- reducing the bus width from a first channel width to a second channel width;
- and
- increasing a number of beats across the single memory channel to maintain a minimum access length (MAL) defined by the DRAM memory system.
A system for conserving power consumption in a memory system, the method comprising:
- means for receiving a memory request from a memory client residing on a system on chip (SoC) for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC via a memory bus comprising a single memory channel;
- means for determining that the memory request from the memory client corresponds to a performance use case for using less than a full width of the memory bus;
- and
- means for conserving memory power consumption for the memory request corresponding to the performance use case by dynamically resizing the memory bus to less than the full width wherein dynamically resizing the memory bus to less than the full width comprises:
- reducing the bus width from a first channel width to a second channel width;
- and
- increasing a number of beats across the single memory channel to maintain a minimum access length (MAL) defined by the DRAM memory system.
A computer program product comprising a computer usable device having a computer readable program code embodied therein, the computer readable program code adapted to be executed to implement a method for conserving power consumption in a memory system, the method comprising:
- receiving a memory request from a memory client residing on a system on chip (SoC) for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC via a memory bus comprising a single memory channel;
- determining that the memory request from the memory client corresponds to a performance use case for using less than a full width of the memory bus;
- and
- conserving memory power consumption for the memory request corresponding to the performance use case by dynamically resizing the memory bus to less than the full width, wherein dynamically resizing the memory bus to less than the full width comprises:
- reducing the bus width from a first channel width to a second channel width;
- and
- increasing a number of beats across the single memory channel to maintain a minimum access length (MAL) defined by the DRAM memory system.
A system for conserving power consumption in a memory system, the system comprising:
- a DRAM memory system;
- and
- a system on chip (SoC) coupled to the DRAM memory system via a memory bus comprising a single memory channel, the SoC comprising one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system, wherein the one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a memory bus width of the memory bus to less than a full width, wherein dynamically resizing the memory bus width to less than the full width comprises reducing the bus width from a first channel width to a second channel width and increasing a number of beats across the single memory channel to maintain a minimum access length (MAL) defined by the DRAM memory system.
Dependencies are inferred from the claim text.