Multi-layer distributed network

A method for preparing a network in an integrated circuit, comprising:

• using a processor, creating a structured test signal network on a non-customizable layer of an integrated circuit the test network having symmetric subnetworks in each quadrant of the integrated circuit wherein each quadrant of the quadrant includes a spine wherein the spine is coupled to a plurality of rows of multiple cells;
• placing a plurality of buffers along the structured test signal network, each of the buffers configurable to route a signal from the structured test signal network to an associated logic cell;
• connecting, using a customizable layer, a first subset of the plurality of buffers to the structured test signal network;
• and
• tying off a second subset of the plurality of buffers, using the customizable layer.

A tangible, non-transient, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method, the method comprising:

• constructing a center test signal network in a non-customizable layer of an integrated circuit, wherein the center test signal network branches into each quadrant of the integrated circuit wherein each quadrant of the quadrant includes a spine wherein the spine is coupled to a plurality of rows of multiple cells;
• constructing a quadrant network in each quadrant of the integrated circuit, the quadrant network in each quadrant having no connectivity to logic elements of the integrated circuit except through a custom layer of the integrated circuit;
• and
• distributing buffers along each quadrant network, wherein each of the buffers is configurable as to routing a signal from the quadrant network to a logic cell of a circuit design and as to tying off in a circuit design that does not use all of the buffers.