Optimized multi-root input output virtualization aware switch

An optimized multi-root input-output virtualization (MRIOV) aware switch comprising:

• a plurality of upstream ports and a plurality of downstream ports, each of the plurality of upstream ports and each of the plurality of downstream ports comprising:
• a media access controller (MAC) configured to negotiate a link width and a link speed for exchange of data packets between a plurality of root complexes and a plurality of I/O devices;
• a clocking module configured to dynamically configure a clock rate of processing data packets based on one or more of the negotiated link width and the negotiated link speed;
• a data link layer (DLL) module coupled to the MAC, configured to operate at the clock rate, wherein the clock rate is indicative of a processing speed;
• an input buffer (IB) module, wherein the IB module is configured to,
• receive data packets from the MAC to be exchanged among the plurality of root complexes and the plurality of I/O devices;
• provide header associated with each of the data packets for identification of destination details associated with the data packets;
• and
• allow storing of transaction layer packets (TLPs) at different memory locations with linked list based addressing and out-of-order reads of the data packets;
• and
• a MRIOV core switching module coupled to the plurality of upstream ports and the plurality of downstream ports, wherein the MRIOV core switching module comprises an upstream arbiter configured to perform arbitration for the data packets exchanged between the plurality of root complexes and the plurality of I/O devices in a multi-host computing system, based on a header code (HC) of the header associated with each of the data packets.