Processing system with interspersed processors with multi-layer interconnect
AssigneeCoherent Logix, Incorporated
InventorsCarl S. Dobbs, Michael R. Trocino, Michael B. Solka
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AssigneeCoherent Logix, Incorporated
InventorsCarl S. Dobbs, Michael R. Trocino, Michael B. Solka
Estimating the term…
Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
An apparatus, comprising:
A method performed by a first configurable communication element in a multiprocessor system, wherein the multiprocessor system comprises a plurality of processors, and a plurality of configurable communication elements interspersed among the plurality of processors, wherein each configurable communication element of the plurality of configurable communication elements includes a local memory coupled to a subset of the plurality of processors and a plurality of routing engines, the method comprising:
A system, comprising:
Dependencies are inferred from the claim text.