Synchronization and order detection in a memory system

A computer implemented method for out-of-synchronization and out-of-order detection in a memory system, the method comprising:

• receiving frames on two or more channels of the memory system at a memory control unit;
• identifying, by the memory control unit, an alignment logic input in each of the received frames;
• generating, by the memory control unit, a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input, the summarized input comprising a combination of tag inputs and memory buffer chip multiple-input shift-register inputs that are separately selected using bit-wise ANDs to apply respective mask values;
• adjusting, by the memory control unit, a timing alignment of the summarized input for each of the channels of the received frames based on a skew value per channel to adjust a relative timing between the tag inputs and the memory buffer chip multiple-input shift-register inputs per channel;
• comparing each of the timing adjusted summarized inputs;
• and
• based on a mismatch between at least two of the timing adjusted summarized inputs, asserting a miscompare signal by the memory control unit.

A computer program product for out-of-synchronization and out-of-order detection in a memory system, the computer program product comprising:

• a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
• receiving frames on two or more channels of the memory system at a memory control unit;
• identifying, by the memory control unit, an alignment logic input in each of the received frames;
• generating, by the memory control unit, a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input, the summarized input comprising a combination of tag inputs and memory buffer chip multiple-input shift-register inputs that are separately selected using bit-wise ANDs to apply respective mask values;
• adjusting, by the memory control unit, a timing alignment of the summarized input for each of the channels of the received frames based on a skew value per channel to adjust a relative timing between the tag inputs and the memory buffer chip multiple-input shift-register inputs per channel;
• comparing each of the timing adjusted summarized inputs;
• and
• based on a mismatch between at least two of the timing adjusted summarized inputs, asserting a miscompare signal by the memory control unit.