Method and system for communicating with non-volatile memory
AssigneeSanDisk Technologies LLC
InventorsGary Lin, Matt Davidson, Milton Barrocas, Aruna Gutta
Life of this patent
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AssigneeSanDisk Technologies LLC
InventorsGary Lin, Matt Davidson, Milton Barrocas, Aruna Gutta
Estimating the term…
Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic. The processor associates each of the plurality of command sequences with a priority, and via the flash interface module, selects one of the plurality of the command sequences based on the priority associated with the one of the plurality of the command sequences and transmits sequentially the first portion of the one of the plurality of the command sequences to either one of the first flash bank or the second flash bank.
A method for managing communication in a flash memory system, the flash memory system comprising a memory controller, a first flash bank and a second flash bank, the first and second flash banks communicatively coupled to the memory controller via a common flash interface, the method comprising the memory controller:
A method for communicating with a first flash bank and a second flash bank via a common flash interface, the method comprising a processor of a memory controller:
The method of 12 wherein the first or second priority depends at least in part on nature of the first command sequence or the another command sequence being a read or write of data.
A memory controller for communicating with a first flash bank and a second flash bank, the memory controller comprising:
Dependencies are inferred from the claim text.