System and method for providing stealth memory
AssigneeMicrosoft Technology Licensing, LLC
InventorsMarcus Peinado, Taesoo Kim
Life of this patent
Estimating the term…
Abstract
The described implementations relate to computer memory. One implementation provides a technique that can include providing stealth memory to an application. The stealth memory can have an associated physical address on a memory device. The technique can also include identifying a cache line of a cache that is mapped to the physical address associated with the stealth page, and locking one or more other physical addresses on the memory device that also map to the cache line.
Claims20
A system comprising:
- two or more processor cores;
- a set associative cache having a plurality of cache lines, each cache line having multiple slots;
- a memory;
- and
- a memory monitor configured to:
- select a physical address on the memory for use by a first one of the two or more processor cores;
- provide a first page of stealth memory to a first application, the first page of stealth memory being located at the selected physical address, wherein the selected physical address is mapped to an individual cache line and loaded into an individual slot of the individual cache line;
- and
- retain the first page of stealth memory in the set associative cache while allowing at least one other physical address to be loaded into another slot of the individual cache line without evicting the selected physical address from the individual slot of the individual cache line.
A method performed on a computer system having a first processor core, a second processor core, and a cache shared by the first processor core and the second processor core, the method comprising:
- providing, to a first application that executes on the first processor core, first stealth memory that maps to an individual cache line of the cache;
- retaining the first stealth memory in a first slot of the individual cache line while allowing at least some other memory to be loaded into a second slot of the individual cache line without evicting the stealth memory from the first slot of the individual cache line;
- and
- preventing the second processor core from accessing the individual cache line.
A system comprising:
- a processing unit including:
- a first processor core,
- a second processor core, and
- a cache having a first cache line with multiple first slots and a second cache line with multiple second slots;
- and
- a memory device having first physical addresses that map to the first cache line and second physical addresses that map to the second cache line,
- the memory storing computer-readable instructions which, when executed by the processing unit, cause the processing unit to:
- restrict the first physical addresses on the memory device for use by the first processor core and not the second processor core;
- provide stealth memory located at an individual first physical address and cause the stealth memory to be stored in an individual first slot of the first cache line;
- and
- retain the stealth memory in the individual first slot of the first cache line while allowing at least some other memory to be loaded into an individual second slot of the first cache line without evicting the stealth memory from the first slot of the individual cache line.
Dependencies are inferred from the claim text.