Multi-core online patching method and apparatus

A multi-core online patching apparatus comprising:

• a memory;
• and
• a processor coupled to the memory and configured to:
• receive a patch, wherein the processor comprises multiple cores;
• separate shared global variables and private global variables defined in the patch;
• and
• map the shared global variables to a shared data segment in a patch area by using a mapping mode of a memory address, wherein the shared global variables are obtained directly from the memory using the memory address, and
• map the private global variables to private data segments in the patch area by using a mapping mode of a cache bus access address,
• wherein the patch area comprises a shared area, a private area, and a backup area,
• wherein the shared area comprises the shared data segment,
• wherein the private area comprises the private data segments,
• wherein, the backup area comprises the private data segments, wherein the private data segments in the backup area restore the private data segments to one of the multiple cores after the one of the multiple cores is reset,
• wherein the private data segments comprise multiple different segments,
• wherein each one of the multiple different segments of the private data segments corresponds to one of the multiple cores of the processor,
• wherein each one of the private global variables corresponds to one of the multiple cores of the processor, and
• wherein the private global variables are mapped to the private data segments according to the multiple cores of the processor.

A non-transitory computer-readable medium having computer executable instructions for performing a method comprising:

• receiving a patch at a processor, wherein the processor comprises multiple cores, and wherein the processor is coupled to a memory;
• separating shared global variables and private global variables defined in the patch;
• mapping the shared global variables to a shared data segment in a patch area by using a mapping mode of a memory address, wherein the shared global variables are obtained directly from the memory using the memory address;
• and
• mapping the private global variables to private data segments in the patch area by using a mapping mode of a cache bus access address,
• wherein the patch area comprises a shared area, a private a, and a backup area,
• wherein the shared area comprises the shared data segment,
• wherein the private area comprises the private data segments,
• wherein the backup area comprises the private data segments, wherein the private data segments in the backup area restore the private data segments to one of the multiple cores after the one of the multiple cores is reset,
• wherein the private data segments comprise multiple different segments,
• wherein each one of the multiple different segments of the private data segments corresponds to one of the multiple cores of the processor,
• wherein each one of the private global variables corresponds to one of the multiple cores of the processor, and
• wherein the private global variables are mapped to the private data segments according to the multiple cores of the processor.