US 9,430,392 B2Granted

Supporting large pages in hardware prefetchers

AssigneeIntel Corporation

InventorsPrabhat Jain, Ashok Jagannathan

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Abstract

Technologies for supporting large pages in hardware prefetchers are described. A processor includes a processor core comprising a pipeline, cache memory and a hardware prefetcher coupled to the processor core and the cache memory. The hardware prefetcher is a region-based hardware prefetcher to track memory regions of a predefined region size that is defined by software to be executed by the processor. The hardware prefetcher is operative to receive incoming requests and track different memory regions of predefined size with multiple streams in a stream table with stream entries. The hardware prefetcher generates a prefetch request and determines whether the prefetch request goes beyond a page boundary of the one memory region. The hardware prefetcher creates a new stream entry to track a successive memory region when the prefetch request goes beyond the page boundary of the one memory region, allowing subsequent prefetch requests to the successive memory region.

Claims20

Dependent claims

A method comprising:

receiving, by a hardware prefetcher, a request from a processor core, wherein the hardware prefetcher is a region-based hardware prefetcher to track memory regions of a predefined region size that is defined by software to be executed by the processor;
tracking, by the hardware prefetcher, a plurality of streams in a stream table with stream entries, wherein each stream entry is to track a different memory region of the predefined region size;
generating, by the hardware prefetcher, a prefetch request to a first memory region;
determining, by the hardware prefetcher, whether the prefetch request goes beyond a page boundary of the first memory region;
generating, by the hardware prefetcher, a rollover request that includes information to create a second stream entry with which to track a successive memory region when the prefetch request goes beyond the page boundary of the first memory region;
determining whether an incoming request is a rollover request;
determining whether there is a page hit in the stream table when the incoming request is a rollover request;
creating, by the hardware prefetcher, the second stream entry in the stream table to track a successive memory region when the prefetch request goes beyond the page boundary of the first memory region;
dropping the rollover request when there is a page hit in the stream table;
generating, by the hardware prefetcher and using the second stream entry, a subsequent prefetch request to the successive memory region;
and
continuing with non-rollover prefetching when the incoming request is not a rollover request.

9 more elements

A processor comprising:

a processor core comprising a pipeline;
cache memory coupled to the processor core;
and
a hardware prefetcher coupled to the processor core and the cache memory, wherein the hardware prefetcher is a region-based hardware prefetcher to track memory regions of a predefined region size;
wherein the hardware prefetcher is to:
receive incoming requests from the pipeline;
track a plurality of streams in a stream table with stream entries, wherein each stream entry is to track a different memory region of the predefined region size;
generate a prefetch request for a cache line in a first memory region tracked by a first stream entry;
determine whether the prefetch request goes beyond a page boundary of the first memory region;
generate a rollover request that includes information to create a second stream entry with which to track a successive memory region when the prefetch request goes beyond the page boundary of the first memory region;
determine whether an incoming request is a rollover request;
determine whether there is a page hit in the stream table when the incoming request is a rollover request;
create the second stream entry in the stream table with the information when there is no page hit in the stream table;
drop the rollover request when there is a page hit in the stream table;
generate, using the second stream entry, a subsequent prefetch request to the successive memory region;
and
continue with non-rollover prefetching when the incoming request is not a rollover request.

14 more elements

A system on chip (SoC) comprising:

a plurality of functional units;
and
shared level-two (L2) cache memory coupled to the plurality of functional units, wherein a first functional unit of the plurality of functional units comprises a L2 hardware prefetcher and a L2 pipeline, wherein the L2 hardware prefetcher is to:
receive incoming requests from the L2 pipeline;
track a plurality of streams in a stream table with stream entries, wherein each stream entry is to track a different memory region of a predefined size;
generate a prefetch request for a cache line in a first memory region tracked by a first stream entry;
determine whether the prefetch request goes beyond a page boundary of the first memory region;
generate a rollover request that includes information to create a second stream entry with which to track a successive memory region when the prefetch request goes beyond the page boundary of the first memory region;
determine whether an incoming request is a rollover request;
determine whether there is a page hit in the stream table when the incoming request is a rollover request;
create the second stream entry in the stream table with the information when there is no page hit in the stream table;
generate, using the second stream entry, a subsequent prefetch request to the successive memory region;
and
continue with non-rollover prefetching when the incoming request is not a rollover request.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/225,715Filed 26 Mar 2014
Published: US 2015/0278099 A11 Oct 2015
Granted: 30 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 12/0862
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with prefetch
G06F 9/3806
For branches, e.g. hedging, branch folding: using address prediction, e.g. return stack, branch history buffer
G06F 9/3812
Instruction prefetching: with instruction modification, e.g. store into instruction stream
G06F 2212/1024
Performance improvement: latency reduction