Prefetch with request for ownership without data
AssigneeIntel Corporation
InventorsJesus Corbal, Lisa K. Wu, George Z. Chrysos, Andrew T. Forsyth, Ramacharan Sundararaman
Life of this patent
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Abstract
A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.
Claims22
A semiconductor chip having multiple processing cores comprising:
- a cache;
- and
- a processing core of said multiple processing cores comprising cache coherence logic to issue a request for ownership of a cache line of the cache without receipt of the cache line in response to the request, said cache coherence logic to give exclusive ownership of the cache line to the processing core in response to only a full write to the cache line, create a dummy entry for said cache line in said cache in response to said request, invalidate said dummy entry in response to only the full write to said cache line, and not invalidate said dummy entry in response to a read of said cache line, wherein said cache coherence logic is to place the dummy entry for said cache line in said cache in an exclusive with no data state of a cache coherency protocol.
A method performed by a processor comprising:
- issuing a request for ownership of a cache line of a cache by a processing core of the processor without receiving the cache line in response to the request;
- giving exclusive ownership of the cache line to the processing core in response to only a full write to the cache line;
- creating a dummy entry for said cache line in said cache in response to the issuing;
- invalidating said dummy entry in response to only the full write to said cache line;
- not invalidating said dummy entry in response to a read of said cache line;
- and
- creating placing the dummy entry for said cache line in said cache in an exclusive with no data state of a cache coherency protocol.
A semiconductor chip having multiple processing cores comprising:
- a processing core of said multiple processing cores comprising its own local cache and cache coherence logic, said cache coherence logic to issue a request for ownership of a cache line without receipt of the cache line in response to the request even if said cache line is not in said local cache, the cache coherence logic to give exclusive ownership of the cache line to the processing core in response to only a full write to the cache line, create a dummy entry for said cache line in said local cache in response to said request, invalidate said dummy entry in response to only the full write to said cache line, and not invalidate said dummy entry in response to a read of said cache line, wherein said cache coherence logic is to place the dummy entry for said cache line in said local cache in an exclusive with no data state of a cache coherency protocol.
A semiconductor chip having multiple processing cores comprising:
- a cache;
- and
- a processing core of said multiple processing cores comprising cache coherence logic to issue a request for ownership of a cache line of the cache without receipt of the cache line in response to the request, said cache coherence logic to give exclusive ownership of the cache line to the processing core in response to only a full write to the cache line, create a dummy entry for said cache line in said cache in response to said request, and place the dummy entry for said cache line in said cache in an exclusive with no data state of a cache coherency protocol.
Dependencies are inferred from the claim text.