Scheduler, multi-core processor system, and scheduling method
AssigneeFujitsu Limited
InventorsHiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
Life of this patent
Estimating the term…
Loading patent…
AssigneeFujitsu Limited
InventorsHiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
Estimating the term…
A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.
A multi-core processor system comprising:
A control method of a multi-core processor system that includes a plurality of cores configured to execute a plurality of tasks, respectively, and a plurality of caches configured to store data accessed by the cores when the cores execute the tasks, respectively, wherein a first core of the cores executes a process comprising:
Dependencies are inferred from the claim text.