Instructions and logic to provide advanced paging capabilities for secure enclave page caches

A processor comprising:

• a first hardware thread and a second hardware thread;
• an enclave page cache to store secure data in a cache line for a shared page address allocated to a corresponding secure enclave accessible by said first and second hardware threads;
• a decode stage to decode a first instruction for execution by said processor, the first instruction specifying said secure enclave as an operand;
• one or more execution units, responsive to the decoded first instruction, to:
• record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave;
• said decode stage to decode a second instruction for execution by said processor, the second instruction specifying said shared page address as an operand;
• and
• one or more execution units, responsive to the decoded second instruction, to:
• mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access secure data corresponding to the shared page address;
• wherein the second instruction is an instruction that specifies said shared page address to prevent the creation of a new translation corresponding to the shared page address in any TLB;
• and
• wherein said one or more execution units, responsive to the decoded second instruction, to:
• decrement the recorded number of hardware threads currently executing in the secure enclave when any of the hardware threads exits the secure enclave.

A method comprising:

• executing, in a multithreaded processor, a first hardware thread and a second hardware thread;
• storing secure data in a cache line for a shared page address allocated to a corresponding secure enclave accessible by said first and second hardware threads;
• decoding a first instruction for execution by said processor, the first instruction specifying said shared page address as an operand;
• responsive to decoding the first instruction, marking an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access secure data corresponding to the shared page address;
• decoding a second instruction for execution by said processor, the second instruction specifying said secure enclave as an operand;
• and
• responsive to decoding the second instruction, recording hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave;
• wherein responsive to decoding the second instruction, the recorded number of hardware threads currently executing in the secure enclave decrements when any of the hardware threads exits the secure enclave.

A method comprising:

• executing, in a multithreaded processor, a first hardware thread and a second hardware thread;
• storing secure data in a cache line for a shared page address allocated to a corresponding secure enclave accessible by said first and second hardware threads;
• decoding a first instruction for execution by said processor, the first instruction specifying said secure enclave as an operand;
• and
• responsive to decoding the first instruction, recording hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave;
• wherein the first instruction is an instruction that specifies said secure enclave to record a number of hardware threads currently executing in the secure enclave;
• wherein responsive to decoding the first instruction, the recorded number of hardware threads currently executing in the secure enclave decrements when any of the hardware threads exits the secure enclave.

A processing system comprising:

• a memory;
• and
• a processor comprising:
• a first hardware thread and a second hardware thread,
• an enclave page cache to store secure data in a cache line for a shared page address allocated to a corresponding secure enclave accessible by said first and second hardware threads,
• a decode stage to decode a first instruction for execution by said processor, the first instruction specifying said shared page address as an operand, and
• one or more execution units, responsive to the decoded first instruction, to mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access secure data corresponding to the shared page address;
• said decode stage to decode a second instruction for execution by said processor, the second instruction specifying said secure enclave as an operand, and
• said one or more execution units, responsive to the decoded second instruction, to
• record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave,
• decrement the recorded number of hardware threads currently executing in the secure enclave when any of the hardware threads exits the secure enclave.