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US 9,430,373 B2Granted
Apparatus including memory channel control circuit and related methods for relaying commands to logical units
AssigneeMicron Technology, Inc.
InventorsDouglas A. Larson, Jeffrey R. Brown
Life of this patent
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Abstract
Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.
Claims16
An apparatus, comprising:
- a switch internal to the apparatus and coupled to a host interface internal to the apparatus;
- and
- non-volatile memory control circuitry internal to the apparatus and coupled to the switch, wherein the non-volatile memory control circuitry includes a channel request queue (CRQ) coupled to a plurality of channel control circuits, which are coupled to a plurality of logical units;
- wherein each of the channel control circuits includes:
- a plurality of logical unit command queues (LCQs);
- and
- a logical unit request queue (LRQ) coupled to the plurality of LCQs;
- wherein each of the channel control circuits is configured to relay a respective erase command to a first one of the plurality of logical units;
- and
- wherein the CRQ is configured to receive a particular command from the host interface via the switch and relay the particular command to a second one of the plurality of logical units via one of the LRQs while the respective erase command is being executed on the first one of the plurality of logical units.
7 more elements
A method, comprising:
- relaying, with a channel control circuit that includes a plurality of logical unit command queues (LCQs) and a logical unit request queue (LRQ) coupled to the plurality of LCQs, an erase command to a first one of a plurality of logical units;
- receiving, with a channel request queue (CRQ) coupled to a plurality of channel control circuits, including the channel control circuit, a particular command from a host via a switch internal to an apparatus, wherein the switch is coupled to a host interface internal to the apparatus and to non-volatile memory control circuitry the includes the CRQ and the plurality of channel control circuits;
- and
- relaying the particular command, with the CRQ, to a second one of the plurality of logical units via one of the LRQs while the erase command is being executed on the first one of the plurality of logical units.
1 more element
A method, comprising:
- receiving a first plurality of commands for a particular logical unit of a plurality of logical units from a host via a switch at a channel request queue (CRQ) coupled to a plurality of channel control circuits, which are coupled to the plurality of logical units, wherein the CRQ and the plurality of channel control circuits are included in the non-volatile memory control circuitry coupled to the switch;
- receiving the second plurality of commands for different logical units of the plurality of logical units from the host via the switch at the CRQ;
- relaying the first plurality of commands via a logical unit request queue (LRQ) to one of a plurality of logical unit command queues (LCQs) associated with the particular logical unit in an order that the first plurality of commands were received, wherein the LRQ and the plurality of LCQs are included in one of the plurality of channel control circuits;
- and
- relaying the second plurality of commands for different logical units via the LRQ to those of the plurality of LCQs associated with the different logical units in an order according to a status of the different logical units.
2 more elements
An apparatus, comprising:
- a switch;
- and
- non-volatile memory control circuitry coupled to the switch, wherein the non-volatile memory control circuitry includes:
- a plurality of channel control circuits, wherein each of the plurality of channel control circuits include:
- a plurality of logical unit command queues (LCQs);
- and
- a logical unit request queue (LRQ) coupled to the plurality of LCQs, wherein the LRQ is configured to:
- relay a first plurality of commands for a particular logical unit to one of the plurality of LCQs associated with the particular logical unit in an order that the first plurality of commands were received;
- and
- relay a second plurality of commands for different logical units to those of the LCQs associated with the different logical units in an order according to a status of the different logical units;
- and
- a channel request queue (CRQ) coupled to the plurality of channel control circuits, wherein the CRQ is configured to receive the second plurality of commands from a host via the switch and relay the command to one of the LRQs.
9 more elements
Dependencies are inferred from the claim text.