Error correction in memory devices by multiple readings with different references

A method for reading a memory device comprising a plurality of memory cells, the method comprising:

• receiving a request of reading a selected data word associated with a selected code word stored in selected memory cells of the plurality thereof with an error correction code;
• reading a first code word representing a first version of the selected code word;
• verifying the first code word according to the error correction code;
• setting the selected code word according to the first code word based upon a positive verification of the first code word;
• reading at least one second code word representing a second version of the selected code word;
• verifying the at least one second code word according to the error correction code;
• and
• setting the selected code word according to the at least one second code word in response to a negative verification of the first code word and to a positive verification of the at least one second code word.

A memory device comprising:

• a plurality of memory cells;
• circuitry configured to receive a request of reading a selected data word associated with a selected code word comprising a plurality of logic values stored in selected memory cells of the plurality of memory cells with an error correction code;
• circuitry configured to read a first code word representing a first version of the selected code word by comparing a state of each selected memory cell with a first reference;
• circuitry configured to verify the first code word according to the error correction code;
• circuitry configured to set the selected code word according to the first code word in response to a positive verification of the first code word;
• circuitry configured to read at least one second code word representing a second version of the selected code word by comparing the state of each selected memory cell with a second reference;
• circuitry configured to verify the second code word according to the error correction code;
• and at least one
• circuitry configured to set the selected code word according to the at least one second code word in response to a negative verification of the first code word and to a positive verification of the at least one second code word.