Data access method, memory control circuit unit and memory storage apparatus

A memory control circuit unit for controlling a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical erasing units, each of the physical erasing units comprising a plurality of physical programming units, and the memory control circuit unit comprising:

• a host interface coupled to a host system;
• a memory interface coupled to the rewritable non-volatile memory module;
• a memory management circuit coupled to the host interface and the memory interface;
• an error checking and correcting circuit coupled to the memory management circuit;
• and
• a data compressing/decompressing circuit coupled to the memory management circuit,
• wherein the data compressing/decompressing circuit fills dummy data to first data to generate second data, the error checking and correcting circuit generates an error checking and correcting code corresponding to the second data, and the memory management circuit further generates an error checking and correcting code frame according to the second data and the error checking and correcting code, issues a command sequence for writing the error checking and correcting code frame into a first physical programming unit among the physical programming units and maps a logical address to the first physical programming unit,
• wherein the memory management circuit receives a read command, wherein the read command instructs to read data from the logical address,
• wherein the memory management circuit issues a command sequence for reading the error checking and correcting code frame from the first physical programming unit to obtain a reading data stream, wherein the reading data stream comprises third data and the error checking and correcting code,
• wherein the memory management circuit adjusts the third data according to a pattern of the dummy data to generate fourth data when the third data cannot be corrected by using the error checking and correcting code to obtain corrected data, and the error checking and correcting circuit uses the error checking and correcting code to correct the fourth data to obtain the corrected data, wherein the corrected data is identical to the second data,
• wherein the memory management circuit removes the dummy data from the corrected data to obtain fifth data.

A memory storage apparatus, comprising:

• a connection interface unit configured to couple to a host system;
• a rewritable non-volatile memory module comprising a plurality of physical erasing units, wherein each of the physical erasing units comprises a plurality of physical programming units;
• and
• a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit fills dummy data to first data to generate second data, generates an error checking and correcting code corresponding to the second data, generates an error checking and correcting code frame according to the second data and the error checking and correcting code, writes the error checking and correcting code frame into a first physical programming unit among the physical programming units, and maps a logical address to the first physical programming unit,
• wherein the memory control circuit unit further receives a read command, wherein the read command instructs to read data from the logical address,
• wherein the memory control circuit unit further reads the error checking and correcting code frame from the first physical programming unit to obtain a reading data stream, and the reading data stream comprises third data and the error checking and correcting code,
• wherein the memory control circuit unit adjusts the third data according to a pattern of the dummy data to generate fourth data when the third data cannot be corrected by using the error checking and correcting code to obtain corrected data, and uses the error checking and correcting code to correct the fourth data to obtain the corrected data, wherein the corrected data is identical to the second data,
• wherein the memory control circuit unit removes the dummy data from the corrected data to obtain fifth data.