Multiple ECC codeword sizes in an SSD

A system, comprising:

• a solid-state non-volatile memory;
• one or more data buffers configured to receive a plurality of host data units for storage in the solid-state non-volatile memory;
• a controller configured to:
• divide the plurality of host data units in the one or more data buffers among a plurality of data payloads, wherein a first data payload comprises a first host data unit and a second data payload comprises a portion of a second host data unit;
• and
• an encoder/decoder configured to:
• encode the first data payload into a first error-correcting code (ECC) codeword having a first codeword size;
• and
• encode the second data payload into a second ECC codeword having a second codeword size, the second codeword size being different from the first codeword size,
• wherein the controller is further configured to write the first ECC codeword and the second ECC codeword to a first page in the solid-state non-volatile memory,
• wherein the first ECC codeword and the second ECC codeword comprise a number of parity bits, and
• wherein the number of parity bits in the first ECC codeword is the same as the number of parity bits in the second ECC codeword.

A non-transitory machine-readable media including instructions thereon that, when executed, perform a method, the method comprising:

• receiving a plurality of host data units for storage in a solid-state non-volatile memory;
• dividing the plurality of host data units among a plurality of data payloads, wherein a first data payload comprises a first host data unit and a second data payload comprises a portion of a second host data unit;
• encoding the first data payload into a first error-correcting code (ECC) codeword having a first codeword size;
• encoding the second data payload into a second ECC codeword having a second codeword size, the second codeword size being different from the first codeword size;
• and
• writing the first ECC codeword and the second ECC codeword to a first page in the solid-state non-volatile memory,
• wherein the first ECC codeword and the second ECC codeword comprise a number of parity bits, and
• wherein the number of parity bits in the first ECC codeword is the same as the number of parity bits in the second ECC codeword.