Method for programming data, memory storage device and memory control circuit unit

A memory storage device, comprising:

• a connection interface unit, configured to be coupled to a host system;
• a rewritable non-volatile memory module, comprising a plurality of physical erasing units, wherein each of the physical erasing units comprises a plurality of physical programming units;
• and
• a memory control circuit unit, coupled with the connection interface unit and the rewritable non-volatile memory module, wherein
• the memory control circuit unit is configured to determine a bit error rate (BER) assessing value of a first physical erasing unit among the physical erasing units according to at least one of erasing count information, writing count information, reading count information, data storage time information and temperature info nation of the first physical erasing unit,
• the memory control circuit unit is further configured to receive a writing command which instructs to write data into at least one of a plurality of logical units, the at least one of the logical units is mapped to a first physical programming unit among the physical programming units, and the first physical programming unit belongs to the first physical erasing unit,
• the memory control circuit unit is further configured to determine whether the first physical erasing unit belongs to a first type physical erasing unit or a second type physical erasing unit according to the determined BER assessing value,
• if the first physical erasing unit belongs to the first type physical erasing unit, the memory control circuit unit is further configured to program the data and the parity code corresponding to the data into the first physical programming unit according to a first code rate, and
• if the first physical erasing unit belongs to the second type physical erasing unit, the memory control circuit unit is further configured to program the data and the parity code corresponding to the data into the first physical programming unit according to a second code rate, wherein the first code rate is higher than the second code rate, wherein the operation of programming the data and the parity code according to the second code rate comprises:
• determining whether a data length of the data is over a data length of N basic management units, wherein N is a positive integer, and a data length of N+1 basic management units is equal to a capacity size of the first physical programming unit;
• if the data length of the data is not over the data length of the N basic management units, programming the data and the parity code corresponding to the data into the first physical programming unit according to the second code rate;
• and
• if the data length of the data is over the data length of the N basic management units, programming a first portion of the data and a first portion of the parity code into the first physical programming unit and programming a second portion of the data and a second portion of the parity code into a second physical programming unit among the physical programming units according to the second code rate.

A memory control circuit unit, for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, and each of the physical erasing units comprises a plurality of physical programming units, the memory control circuit unit comprising:

• a host interface, configured to be coupled to a host system;
• a memory interface, configured to be coupled to the rewritable non-volatile memory module;
• an error checking and correcting (ECC) circuit;
• and
• a memory management circuit, coupled with the host interface, the memory interface and the ECC circuit, wherein
• the memory management circuit is configured to determine a bit error rate (BER) assessing value of a first physical erasing unit among the physical erasing units according to at least one of erasing count information, writing count information, reading count information, data storage time information and temperature information of the first physical erasing unit,
• the memory management circuit is further configured to receive a writing command which instructs to write data into at least one of a plurality of logical units, the at least one of the logical units is mapped to a first physical programming unit among the physical programming units, and the first physical programming unit belongs to the first physical erasing unit,
• the memory management circuit is further configured to determine whether the first physical erasing unit belongs to a first type physical erasing unit or a second type physical erasing unit according to the determined BER assessing value,
• if the first physical erasing unit belongs to the first type physical erasing unit, the memory management circuit is further configured to send a first command sequence which instructs to program the data and the parity code corresponding to the data into the first physical programming unit according to a first code rate,
• if the first physical erasing unit belongs to the second type physical erasing unit, the memory management circuit is further configured to send a second command sequence which instructs to program the data and the parity code corresponding to the data into the first physical programming unit according to a second code rate, wherein the first code rate is higher than the second code rate, wherein the operation of sending the second command sequence comprises:
• determining whether a data length of the data is over a data length of N basic management units, wherein N is a positive integer, and a data length of N+1 basic management units is equal to a capacity size of the first physical programming unit,
• if the data length of the data is not over the data length of the N basic management units, sending the second command sequence to instruct to program the data and the parity code corresponding to the data into the first physical programming unit only according to the second code rate, and
• when the data length of the data is over the data length of the N basic management units, sending the second command sequence to instruct to program a first portion of the data and a first portion of the parity code into the first physical programming unit and to program a second portion of the data and a second portion of the parity code into a second physical programming unit among the physical programming units according to the second code rate.