Memory program upon system failure
AssigneeCypress Semiconductor Corporation
InventorsSunil Atri, Cliff Zitlaw
Life of this patent
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Abstract
A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero. Further, the system can include a processing unit configured to provide the timer value to the timer device and the memory address information to the register.
Claims14
A system comprising:
- a timer device integrated on a host device;
- a buffer, integrated on an another device, configured to receive debug data representative of one or more probed nodes in the system;
- a register, integrated on the another device, configured to receive memory address information;
- and
- a memory device, integrated on the another device, configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero, wherein the buffer is configured to transfer the debug data to the memory device in response to a system failure program command issued on a dedicated line.
A method comprising:
- receiving debug data in a buffer;
- receiving memory address information in a register;
- and
- storing, in a memory device, the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of a timer device reaches zero, wherein the debug data is representative of one or more probed nodes in a system comprising the buffer, register, memory device, and timer device, wherein the timer device is integrated on a host device, wherein the buffer, the register, and the memory device are integrated on another device, and wherein the storing comprises receiving, at the memory device, the debug data from the buffer;
- and
- transmitting the debug data in the buffer to the memory device in response to a system failure program command issued on a dedicated line.
Dependencies are inferred from the claim text.