# US 9,430,254 B2 · Register mapping techniques

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- Number: US 9,430,254 B2
- Document ID: US9430254B2
- Status: Granted
- Kind: B2
- Application number: 13/727,474
- Filed: 2012-12-26
- Published: 2013-06-27
- Granted: 2016-08-30
- Earliest claimed: 2011-12-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Masanori Mitsugi; Hiroyuki Tanaka; Nobuyoshi Tanaka
- Web page: https://patentgrep.com/patent/US9430254B2

## CPC

- G06F 9/455: Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F 9/45533: {Hypervisors; Virtual machine monitors}
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/5077: {Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A technique for register mapping in a virtual system includes preparing a register pool that includes a plurality of registers for mapping. A mapping table is prepared that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers. At the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation is acquired. One of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, is set as a mapped register to be accessed per the register access request.

## Claims

### Claim 1

A computer program product, comprising:
a computer-readable storage medium; and
code embodied on the computer-readable storage medium for register mapping in a virtual system that implements a hypervisor and at least two operating systems that are operable while executing at least two hardware threads, wherein the code, when executed by a data processing system, is configured to:
prepare a register pool that includes a plurality of registers for mapping;
prepare a mapping table that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers;
acquire, at the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation; and
set one of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, as a mapped register to be accessed per the register access request, wherein the plurality of parameters that express the operational state within the mapping table include an operation ID that expresses whether the hypervisor is operating or an operating system (OS) is operating, an ID for each OS, and an ID for each hardware thread.

### Claim 2 (depends on 1)

The computer program product of claim 1, wherein the mapping table includes, for each of the registers that is mapped, a check mask for specifying what parameter information is used to check whether or not there is the match with the parameters selected from among the operation ID, the ID for OS, and the ID for the hardware thread.

### Claim 3 (depends on 2)

The computer program product of claim 2, wherein the setting the register to be accessed per the register access request includes determining whether or not there is a match of the information for the parameters specified by the check mask within the mapping table.

### Claim 4 (depends on 1)

The computer program product of claim 1, wherein, in response to the information for the acquired register ID not matching the information for a register ID within the mapping table, a register other than one of the registers within the register pool is set as the register to be accessed per the register access request.

### Claim 5 (depends on 2)

The computer program product of claim 2, wherein, in response to the information for the acquired register ID not matching the information for a register ID within the mapping table, a register other than one of the registers within the register pool is set as the register to be accessed per the register access request.

### Claim 6

A data processing system, comprising:
a memory; and
a processor coupled to the memory, wherein the processor is configured to:
prepare a register pool that includes a plurality of registers for mapping;
prepare a mapping table that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers;
acquire, at the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation; and
set one of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, as a mapped register to be accessed per the register access request, wherein the plurality of parameters that express the operational state within the mapping table include an operation ID that expresses whether the hypervisor is operating or an operating system (OS) is operating, an ID for each OS, and an ID for each hardware thread.

### Claim 7 (depends on 6)

The data processing system of claim 6, wherein the mapping table includes, for each of the registers that is mapped, a check mask for specifying what parameter information is used to check whether or not there is the match with the parameters selected from among the operation ID, the ID for OS, and the ID for the hardware thread.

### Claim 8 (depends on 7)

The data processing system of claim 7, wherein the setting the register to be accessed per the register access request includes determining whether or not there is a match of the information for the parameters specified by the check mask within the mapping table.