Run-time code parallelization using out-of-order renaming with pre-allocation of physical registers

A processor, comprising:

• a hardware-implemented pipeline, configured to process a sequence of instructions of program code that are specified using one or more architectural registers, including renaming the architectural registers in the instructions so as to produce operations specified using one or more physical registers;
• and
• parallelization circuitry, configured to select at least first and second segments of the sequence of instructions, wherein the second segment occurs later in the sequence than the first segment, and to rename one or more of the architectural registers in the instructions of the second segment, before completing renaming the architectural registers in the instructions of the first segment, by:
• identifying an architectural register that is written-to by the instructions of the first segment;
• when renaming the first segment, forcing a last write operation to the identified architectural register in the first segment to be mapped to a given physical register;
• and
• when renaming the second segment, before completing the renaming in the first segment, forcing a first readout operation from the identified architectural register in the second segment to be mapped to the same given physical register.