Semi-exclusive second-level branch target buffer

A system for a semi-exclusive second-level branch target buffer, the system comprising:

• a first-level branch target buffer (BTB1);
• a branch target buffer preload table (BTBP), wherein the BTBP is smaller than the BTB1 and is searched in parallel with the BTB1 to predict a branch instruction target;
• a second-level branch target buffer (BTB2), wherein the BTB2 is larger than the BTB1;
• and
• a processing circuit coupled to the BTB1, the BTBP, and the BTB2, the processing circuit configured to perform:
• searching to locate a plurality of entries in the BTB2 having a memory region corresponding to a search request;
• based on locating the entries in the BTB2, performing a bulk transfer of a plurality of located entries from the BTB2 to the BTBP;
• updating, by the processing circuit, a state associated with the located entries from the BTB2 to encourage exclusivity between the BTB1 and the BTB2 by marking the located entries in the BTB2 as least recently used to force an age status change and decrease a potential lifespan of the located entries in the BTB2 based on transferring the located entries from the BTB2 to the BTBP;
• based on transferring a BTBP entry from the BTBP to the BTB1, evicting, by the processing circuit, a BTB1 entry from the BTB1;
• transferring the evicted BTB1 entry from the BTB1 to the BTB2;
• upon a BTB2 hit, storing BTB2 hit location information comprising a BTB2 column number in the BTBP;
• and
• upon a prediction from the BTBP of an entry having the BTB2 as an install source, performing the updating of the state associated with a corresponding BTB2 entry of the located entries from the BTB2.