Sharing register file read ports for multiple operand instructions

A computer system, comprising:

• memory to store a plurality of instructions;
• and
• a central processing unit, comprising:
• a register file having a plurality of read ports;
• a first execution unit having a first plurality of input ports;
• multiplexers to selectively couple different arrangements of the plurality of read ports to the first plurality of input ports;
• a first scheduler circuit to receive at least a subset of the plurality of instructions, schedule a first instruct on from the subset in the first execution unit, and control the multiplexers to select arrangements for coupling the plurality of read ports to the first plurality of input ports based on a type of the first instruction;
• a second execution unit having a second plurality of input ports, wherein a first subset of the plurality of read ports is associated with the first plurality of input ports of the first execution unit and a second subset of the plurality of read ports is associated with the second plurality of input ports of the second execution unit;
• and
• a second scheduler circuit to schedule instructions for the second execution unit, wherein the first scheduler circuit is to control the multiplexers to route at least one of the plurality of read ports in the second subset to one of the first plurality of input ports and is to instruct the second scheduler circuit to delay instructions scheduled for the second execution unit by inserting a bubble between the instructions scheduled for the second execution unit while the multiplexers are configured to route at least one of the plurality of read ports in the second subset to one of the first plurality of input ports.

A method for reading operands from a register file having a plurality of read ports by a first execution unit having a first plurality of input ports, comprising:

• scheduling an instruction to be executed by the first execution unit using a first scheduler circuit associated with the first execution unit, wherein a first subset of the plurality of read ports is associated with the first plurality of input ports of the first execution unit, and a second subset of the plurality of read ports is associated with a second plurality of input ports of a second execution unit having a second scheduler circuit;
• selectively coupling a particular arrangement of the plurality of read ports to the first plurality of input ports based on a type of the instruction by routing at least one of the plurality of read ports in the second subset to one of the first plurality of input ports;
• and
• sending a signal from the first scheduler circuit to the second scheduler circuit to instruct the second scheduler circuit to delay instructions scheduled for the second execution unit by inserting a bubble between the instructions scheduled for the second execution unit while the at least one of the plurality of read ports in the second subset is routed to one of the first plurality of input ports.