Scalar optimizations for shaders
AssigneeMicrosoft Technology Licensing, LLC
InventorsAndy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
Life of this patent
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Abstract
Described herein are optimizations of thread loop intermediate representation (IR) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop. Another embodiment involves reducing the size of a thread loop trip for a commonly-found case where a piece of compute shader is executed by a single thread (or a compiler-analyzable range of threads). In yet another embodiment, compute shader thread indices are cached to avoid excessive divisions, further improving execution speed.
Claims15
A method of optimizing intermediate representation (IR) code comprising a plurality of thread loops, the method performed by a computing device comprised of storage hardware and processing hardware, the method comprising:
- receiving the IR code and storing the IR code in the storage hardware, the IR code comprising the thread loops, wherein the thread loops were generated by replacing corresponding thread blocks during de-parallelization of original IR code comprised of the thread blocks, the thread loops of the IR code comprising temporary scalar variables and operations therewith generated and inserted into the IR code during the de-parallelization of the thread blocks of the original IR code;
- performing, by the processing hardware, data-flow analysis on the received IR code to identify, among the temporary scalar variables, any temporary scalar variables within thread loops and at beginnings or ends of thread loops that, according to the entirety of the IR code including the operations in the thread blocks, are temporary scalar variables that need to be loaded at the beginning of thread loops and stored on exit from thread loops;
- and
- according to the data-flow analysis, updating, by the processing hardware, the IR code in the storage hardware, to remove load operations and store operations of the identified temporary scalar variables, wherein the updated IR code is compiled to be executed by a central processing unit (CPU).
A method of optimizing compute shader thread indices to reduce divisions thereof, the method performed for converting parallel code for a GPU to code for a CPU, the parallel code comprising a thread block and a compute shader within the thread block, the thread block comprising up to three dimensions with respective bounds, the method performed by a computing device comprised of processing hardware and storage hardware, the method, when converting the parallel code to code for a CPU, comprising:
- providing a thread index stored in the storage hardware, the thread index used for addressing threads in the thread block;
- pre-computing, by the processing hardware, a plurality of thread index arrays and storing in the storage hardware the thread index arrays as part of a state of the compute shader, wherein the thread index arrays are available to any thread block of the compute shader in executing the compute shader, and a plurality of thread blocks of the compute shader use the thread index arrays to execute the compute shader;
- and
- using the thread index arrays by the processing hardware to reconstruct the thread index via accesses to the thread index arrays, wherein a thread index array is pre-computed such that, for a given thread index of one dimension and a given corresponding thread index array, an array element at any given index contains a thread identifier computed according to corresponding thread identifiers of the other dimensions, respectively.
Dependencies are inferred from the claim text.