Fused multiply add pipeline
AssigneeInternational Business Machines Corporation
InventorsSon Dao Trong, Michael Klein, Christophe Layer, Silvia M. Mueller
Life of this patent
Estimating the term…
Abstract
A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor is disclosed. A multiplication is initially performed between a first operand and a second operand in a multiplier block to obtain a set of partial product results. The partial product results are sent to a carry-save adder block. A partial product reduction is performed on the partial product results to generate a carry-save result having a sum term and a carry term. The carry-save result is then formatted to generate a carry-out bit. The carry-save result is added to a third operand to generate a final result.
Claims20
A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor, said method comprising:
- performing a multiplication between a first operand and a second operand in a multiplier block to obtain a set of partial product results;
- inputting said partial product results to a carry-save adder block;
- performing a partial product reduction of said partial product results to generate a carry-save result having a sum term and a carry term;
- performing an XNOR operation on the sixth most significant bit of said sum term and the six most significant bit of said carry term of said carry-save result to generate a carry-out bit;
- adding said carry-save result to a third operand to generate a sum;
- and
- generating a final result by combining said carry-out bit to said sum.
A computer-readable device having a computer program product for operating a fused-multiply-add pipeline in a floating-point unit of a processor, said computer-readable device comprising:
- program code for performing a multiplication between a first operand and a second operand in a multiplier block to obtain a set of partial product results;
- program code for inputting said partial product results to a carry-save adder block;
- program code for performing a partial product reduction of said partial product results to generate a carry-save result having a sum term and a carry term;
- program code for performing an XNOR operation on the sixth most significant bit of said sum term and the six most significant bit of said carry term of said carry-save result to generate a carry-out bit;
- program code for adding said carry-save result to a third operand to generate a sum;
- and
- program code r generating a final result by combining said carry-out bit to said sum.
A processor having a fused-multiply-add pipeline within a floating-point unit, said processor comprising:
- a multiplier for multiplying a first operand and a second operand to obtain a set of partial product results;
- a carry-save adder for performing a partial product reduction on said partial product results to generate a carry-save result having a sum term and a carry term;
- an aligner for performing an XNOR operation on the sixth most significant bit of said sum term and the six most significant bit of said carry term of said carry-save result to generate a carry-out bit;
- an adder for adding said carry-save result to a third operand to generate a sum, and for generating a final result by combining said carry-out bit to said sum.
Dependencies are inferred from the claim text.