Method for protecting a cryptographic device against SPA, DPA and time attacks
AssigneeSTMicroelectronics International N.V.
InventorsGiovanni Di Sirio, Giovanni Fontana
Life of this patent
Estimating the term…
Abstract
A method is for operating a cryptographic device to reduce effects of power analysis and time attacks. The method may include executing a first set of cryptographic algorithm computations with a first crypto-processor of the cryptographic device. The first set of cryptographic algorithm computations may provide encryption of a first set of data to be protected with a first secret key stored in the cryptographic device. The method may further include executing a second set of cryptographic algorithm computations with a second crypto-processor of the cryptographic device for providing encryption of a second set of data different from the first set of data to be protected with a second different secret key.
Claims30
A method of operating a cryptographic device to reduce effects of power analysis attacks, the method comprising:
- splitting cryptographic computations in the cryptographic device into a first set of cryptographic algorithm computations and a second set of cryptographic algorithm computations and pseudo-randomly assigning the first and second sets of cryptographic algorithm computations to a first crypto-processor and at least one second crypto-processor;
- executing the first set of cryptographic algorithm computations with the first crypto-processor of the cryptographic device, the first set of cryptographic algorithm computations providing encryption of a first set of data to be protected with a first secret key;
- executing the second set of cryptographic algorithm computations with the at least one second crypto-processor of the cryptographic device for providing encryption of a second set of data different from the first set of data to be protected with a second different secret key;
- and
- generating varying power consumption from the first crypto-processor and the at least one second crypto-processor respectively based upon the execution of the first and second sets of cryptographic algorithm computations, thereby reducing the effects of power analysis attacks.
A method of operating a cryptographic device to reduce effects of power analysis attacks, the method comprising:
- splitting cryptographic computations in the cryptographic device into a first set of cryptographic algorithm computations and a second set of cryptographic algorithm computations and pseudo-randomly assigning the first and second sets of cryptographic algorithm computations to a first crypto-processor and at least one second crypto-processor;
- executing the first set of cryptographic algorithm computations with the first crypto-processor of the cryptographic device, the first set of cryptographic algorithm computations providing encryption of a first set of data to be protected with a first secret key stored in the cryptographic device;
- independently generating a second different secret key in the cryptographic device;
- executing the second set of cryptographic algorithm computations with the at least one second crypto-processor of the cryptographic device for providing encryption of a second set of data different from the first set of data to be protected with the second different secret key, the execution of the first and second sets of cryptographic algorithm computations being simultaneous with each other;
- and
- generating varying power consumption from the first crypto-processor and the at least one second crypto-processor respectively based upon the execution of the first and second sets of cryptographic algorithm computations, thereby reducing the effects of power analysis attacks.
An integrated circuit (IC) card to be inserted into a cryptographic device, the IC Card comprising:
- a terminal pin;
- a first crypto-processor and at least one second crypto-processor associated with said terminal pin;
- and
- a central processing unit (CPU) associated with said terminal pin and configured to split cryptographic computations into a first set of cryptographic algorithm computations and a second set of cryptographic algorithm computations, and pseudo-randomly assign the first and second sets of cryptographic algorithm computations to said first crypto-processor and said at least one second crypto-processor;
- said first crypto-processor configured to execute the first set of cryptographic algorithm computations for providing encryption of a first set of data to be protected with a first secret key;
- and
- said at least one second crypto-processor configured to execute the second set of cryptographic algorithm computations for providing encryption of a second set of data different from the first set of data to be protected with a second different secret key;
- said first crypto-processor and said at least one second crypto-processor configured to generate varying power consumption respectively based upon the execution of the first and second sets of cryptographic algorithm computations, thereby reducing effects of power analysis attacks.
A circuit on an integrated circuit (IC) card to be inserted into a cryptographic device, the circuit comprising:
- a first crypto-processor and at least one second crypto-processor;
- and
- a central processing unit (CPU) configured to
- split cryptographic computations into a first set of cryptographic algorithm computations and a second set of cryptographic algorithm computations, and
- pseudo-randomly assign the first and second sets of cryptographic algorithm computations to said first crypto-processor and said at least one second crypto-processor;
- said first crypto-processor configured to execute the first set of cryptographic algorithm computations for providing encryption of a first set of data to be protected with a first secret key;
- and
- said at least one second crypto-processor configured to execute the second set of cryptographic algorithm computations for providing encryption of a second set of data different from the first set of data to be protected with a second different secret key;
- said first crypto-processor and said at least one second crypto-processor configured to generate varying power consumption respectively based upon the execution of the first and second sets of cryptographic algorithm computations, thereby reducing effects of power analysis attacks.
Dependencies are inferred from the claim text.