Interaction of transactional storage accesses with other atomic semantics
AssigneeInternational Business Machines Corporation
InventorsBradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams
Life of this patent
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Abstract
In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail.
Claims26
A method of data processing in a data processing system, the method comprising:
- in a processor, detecting an instruction sequence of a particular thread including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block;
- and
- in response to detecting the instruction sequence within the particular thread, the processor causing the conditional write access to the target memory block to fail.
A processing unit, comprising integrated circuitry, the integrated circuitry including:
- at least one execution unit that executes an instruction sequence of a particular thread;
- and
- logic that detects in the instruction sequence of the particular thread, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block, and that, responsive to detecting the instruction sequence within the particular thread, causes the conditional write access to the target memory block to fail.
A design structure tangibly embodied in a non-transitory machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
- a processing unit, including:
- at least one execution unit that executes an instruction sequence of a particular thread;
- and
- logic that detects in the instruction sequence of the particular thread, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block, and that, responsive to detecting the instruction sequence, causes the conditional write access to the target memory block to fail.
Dependencies are inferred from the claim text.