Power-management for integrated circuits
AssigneeRambus Inc.
InventorsIan Shaeffer, Lei Luo, Liji Gopalakrishnan
Life of this patent
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Abstract
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
Claims20
An integrated circuit comprising:
- a memory array;
- a control interface to receive, synchronously with respect to a first timing signal, commands for accessing the memory array;
- a data interface to receive, synchronously with respect to a second timing signal, write data destined for storage within the memory array in association with one or more of the commands;
- and
- enable circuitry to independently enable and disable distribution of the first and second timing signals to the control interface and the data interface, respectively, such that distribution of one of the first and second timing signals may be enabled while distribution of the other of the first and second timing signals is disabled.
A method of operation within an integrated circuit, the method comprising:
- receiving commands via a control interface of the integrated circuit synchronously with respect to a first timing signal, the commands specifying respective operations within a memory array of the integrated circuit;
- receiving write data via a data interface of the integrated circuit synchronously with respect to a second timing signal, the write data destined for storage within the memory array in association with one or more of the commands;
- and
- independently enabling and disabling distribution of the first and second timing signals to the control interface and the data interface, respectively, such that distribution of one of the first and second timing signals may be enabled while distribution of the other of the first and second timing signals is disabled.
An integrated circuit comprising:
- a memory array;
- means for receiving commands synchronously with respect to a first timing signal, the commands specifying respective operations within the memory array;
- means for receiving write data synchronously with respect to a second timing signal, the write data destined for storage within the memory array in association with one or more of the commands;
- and
- means for independently enabling and disabling distribution of the first and second timing signals to the means for receiving commands and the means for receiving write data, respectively, such that distribution of one of the first and second timing signals may be enabled while distribution of the other of the first and second timing signals is disabled.
Dependencies are inferred from the claim text.