System and method for idle state optimization in a multi-processor system on a chip

A computer system for idle state optimization in a portable computing device (“PCD”), the system comprising:

• a CPU operative to execute computer readable program code stored in a non-transitory computer usable medium to control an idle state selection (“ISS”) module and cause the ISS module to:
• receive a power budget, wherein the power budget represents a maximum aggregate power consumption level for a plurality of processing cores;
• determine a current aggregate power consumption level for the plurality of processing cores;
• compare the current aggregate power consumption level with the power budget;
• and
• if the current aggregate power consumption level is less than the power budget, transition at least one eligible processing core from a first idle state to a second idle state, wherein a latency value associated with the at least one eligible processing core is reduced by virtue of the transition from the first idle state to the second idle state.

A computer system for idle state optimization in a portable computing device (“PCD”), the system comprising:

• a CPU operative to execute computer readable program code stored in a non-transitory computer usable medium to control:
• a means for receiving a power budget, wherein the power budget represents a maximum aggregate power consumption level for a plurality of processing cores;
• a means for determining a current aggregate power consumption level for the plurality of processing cores;
• a means for comparing the current aggregate power consumption level with the power budget;
• and
• if the current aggregate power consumption level is less than the power budget, a means for transitioning at least one eligible processing core from a first idle state to a second idle state, wherein a latency value associated with the at least one eligible processing core is reduced by virtue of the transition from the first idle state to the second idle state.

A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for idle state optimization in a portable computing device (“PCD”), said method comprising:

• receiving a power budget, wherein the power budget represents a maximum aggregate power consumption level for a plurality of processing cores;
• determining a current aggregate power consumption level for the plurality of processing cores;
• comparing the current aggregate power consumption level with the power budget;
• and
• if the current aggregate power consumption level is less than the power budget, transitioning at least one eligible processing core from a first idle state to a second idle state, wherein a latency value associated with the at least one eligible processing core is reduced by virtue of the transition from the first idle state to the second idle state.