System clock distribution in a distributed computing environment
AssigneeAdvanced Processor Architectures, LLC
InventorsLouis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
Life of this patent
Estimating the term…
Abstract
A system clock signal distributed to electronic configurable and reconfigurable computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers (DDCC), include input addressable data/clock ports on which system clock signals are accepted and may be propagated on one or more data/clock output ports. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.
Claims30
A method of distributing a system clock signal within a distributed computing system, the method comprising:
- receiving a system clock signal of a first frequency from a clock source;
- providing the system clock signal to a first die of a plurality of interconnected die via a first input port of the first die;
- providing a copy of the system clock signal from the first die to a second die of the plurality of die via a first input port of the second die;
- sending a first signal comprising data from the first die to the second die over a send line of the first die, the send line of the first die configured to send data without receiving data;
- and
- receiving an acknowledgement signal at the first die, the acknowledgement signal received from the second die over the send line of the first die,
- wherein at least some of the plurality of interconnected die receive a master primary clock signal of the first frequency, wherein the master primary clock signal is based on the system clock signal, and wherein the master primary clock signal is distributed to the at least some of the plurality of interconnected die according to a system clock distribution network, and
- wherein at least one of the first die or the second die comprises a hardware processor.
A method of distributing a system clock signal within a distributed computing system, the method comprising:
- receiving a system clock signal of a first frequency from a clock source;
- providing the system clock signal to a first die of a plurality of interconnected die via a first input port of the first die;
- superimposing a data signal on a copy of the system clock signal;
- and
- providing the copy of the system clock signal with the superimposed data signal from the first die to a second die of the plurality of die via a first input port of the second die,
- wherein at least some of the plurality of interconnected die receive a master primary clock signal of the first frequency, wherein the master primary clock signal is based on the system clock signal, and wherein the master primary clock signal is distributed to the at least some of the plurality of interconnected die according to a system clock distribution network, and
- wherein at least one of the first die or the second die comprise a memory chip.
A computing system comprising:
- a system clock reception port configured to receive a system clock signal and provide the system clock signal over a first input line to at least one die of a dual die chip carrier (DDCC);
- and
- a plurality of interconnected DDCCs comprising:
- a first DDCC die having a plurality of input ports and a plurality of output ports, at least one input port from the plurality of input ports configured to receive a copy of the system clock from the system clock generator, wherein at least some of the plurality of input ports are independently configurable, wherein at least some of the plurality of output ports are independently configurable, and wherein at least one of the plurality of output ports is configured to output a master primary clock signal or a master secondary clock signal based on the copy of the system clock signal;
- and
- a second DDCC die having a plurality of input ports and a plurality of output ports, the second DDCC die being configured to receive the master primary clock signal or the master secondary clock signal at one of the input ports of the plurality of input ports of the second DDCC die,
- wherein the master primary clock signal of the first DDCC die remains active during system operation.
Dependencies are inferred from the claim text.