CPU current ripple and OCV effect mitigation

A processor, comprising:

• a clock generator circuit operative to generate at least first and second clock signals, the second clock signal having the same frequency, but a phase offset, relative to the first clock signal;
• a first functional unit of the processor clocked with the first clock signal;
• a second functional unit of the processor clocked with the second clock signal;
• and
• a clock phase synchronization circuit interposed on a data path between the second functional unit and a circuit, other than the first functional unit, that is clocked by the first clock signal and operative to synchronize data transfer between the second functional unit and a circuit clocked by the first clock signal;
• wherein the clock generator circuit is further operative to suspend at least one of the first and second clock signals when the associated functional unit of the processor is placed in an inactive state.

An On-Chip Variation (OCV) mitigation First In First Out (FIFO) memory circuit operative to synchronize data between clock phase domains wherein clock signals have the same frequency but different relative phases, and further operative to mitigate the effects of OCV in clock signals, comprising:

• in a first clock phase domain,
• inputs operative to receive a first clock signal and a plurality of first strobe signals, each first strobe signal operative to qualify a cycle of the first clock signal;
• a plurality of data storage registers;
• source pointer logic operative to generate write pointers into the data storage registers and to output a plurality of write pointers;
• a plurality of write pointer registers, each associated with and qualified by a first strobe signal and operative to receive a write pointer from the source pointer logic and output a write pointer to a second clock phase domain of the OCV mitigation FIFO;
• and
• a read pointer multiplexer operative to receive the plurality of first strobe signals and a plurality of read pointers from the second clock phase domain of the OCV mitigation FIFO and output an active read pointer to the source pointer logic based on the first strobe signals;
• and
• in a second clock phase domain wherein clock signals have the same frequency as, but different relative phases than, clock signals in the first clock phase domain,
• inputs operative to receive a second clock signal having a phase offset from the first clock signal and a plurality of second strobe signals, each second strobe signal operative to qualify a cycle of the second clock signal associated with a corresponding cycle of the first clock signal;
• target pointer logic operative to generate a plurality of read pointers;
• a plurality of read pointer registers, each associated with and qualified by a second strobe signal and operative to receive a read pointer from the target pointer logic and output a read pointer to the first clock phase domain of the OCV mitigation FIFO;
• and
• a write pointer multiplexer operative to receive the plurality of second strobe signals and a plurality of write pointers from the first clock phase domain of the OCV mitigation FIFO and output an active write pointer to the target pointer logic based on the second strobe signals;
• and
• a data multiplexer operative to receive data from the first clock phase domain of the OCV mitigation FIFO and output data based on a read pointer received from the target pointer logic.