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US 9,429,623 B2Granted
Solution for full speed, parallel DUT testing
AssigneeAdvantest Corporation
InventorsW Scott Villareal Filler, Ahmed S. Tantawy, Erik H. Volkerink
Life of this patent
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Abstract
A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT.
Claims19
A system for use in automated test equipment, the system comprising:
- a configurable integrated circuit (IC) including a plurality of testers, wherein each tester connects to a single data storage device under test to perform fully speed deterministic testing and includes
- a functional acceleration block including,
- pattern generation logic to generate write data based upon test patterns;
- receiver logic to receive read data;
- and
- hardware implemented comparison logic to compare the write data and corresponding read data;
- and
- an interface protocol core, wherein each interface protocol core is directly connected to the pattern generation logic of a respective functional acceleration block using dedicated bus links, wherein one or more data storage devices under test are removably directly connected to respective ones of the plurality of interface cores, and wherein the interface cores wraps storage command into a standard protocol for transmission over a physical channel as electrical signals to send the write data to storage locations in the storage device under test and receive the corresponding read data from the storage locations in the storage device under test.
5 more elements
An apparatus comprising:
- a configurable integrated circuit (IC) for testing data storage device, wherein the configurable IC includes a plurality of testers implemented by an array of programmable logic blocks and a hierarch of reconfigurable interconnects, each tester including,
- a functional acceleration block including,
- pattern generation logic to generate write data based upon test patterns;
- receiver logic to receive read data;
- and
- comparison logic to compare the write data and corresponding read data;
- and
- an interface protocol core that directly connects a single storage devices under test to the test pattern generation logic of the respective functional acceleration block of the tester using dedicated bus links, wherein the interface cores send the write data to storage locations in the data storage device under test and receive the corresponding read data from the storage location in the data storage device under test, and
- wherein each functional acceleration block and corresponding interface core are in close proximity to a respective data storage device under test to allow optimized connectivity with regards to minimal management overhead, matched bandwidth and latency to avoid bottlenecks and to allow communication with the data storage device under test at maximum speed.
6 more elements
Dependencies are inferred from the claim text.