Reliability test screen optimization
AssigneeGlobalfoundries Inc.
InventorsTheodoros E. Anemikos, Jeanne P. Bickford, Douglas S. Dewey, Ernest A. Viau, Jr.
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AssigneeGlobalfoundries Inc.
InventorsTheodoros E. Anemikos, Jeanne P. Bickford, Douglas S. Dewey, Ernest A. Viau, Jr.
Estimating the term…
Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.
A method of optimizing power usage in an integrated circuit design, said method comprising:
A method of optimizing power usage in an integrated circuit design, said method comprising:
A method of optimizing power usage in an integrated circuit design, said method comprising:
A testing system comprising:
A non-transitory computer storage medium storing instructions and being readable by a computerized device, said instructions causing said computerized device to perform a method of optimizing power usage in an integrated circuit design, said method comprising:
Dependencies are inferred from the claim text.