Semiconductor integrated circuit device having function for detecting degradation of semiconductor device and method of driving the same
AssigneeSK hynix Inc.
InventorJeong Tae Hwang
Life of this patent
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Abstract
A semiconductor integrated circuit device having a function for detecting degradation of a semiconductor device and a method of driving the same are disclosed. The semiconductor integrated circuit device includes an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor, a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor, and a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor.
Claims27
A semiconductor integrated circuit device comprising:
- an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor;
- a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor;
- a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor,
- a first output terminal unit withdrawn from a connection node of the PMOS transistor and the NMOS transistor;
- a second output terminal unit electrically coupled to a source of the PMOS transistor;
- and
- a loop forming unit configured to electrically couple the second output terminal unit and a source of the NMOS transistor,
- wherein the first and second output terminals and the loop forming unit are configured to measure a current value of a first current path flowing through the PMOS transistor and a current value of a second current path flowing through the NMOS transistor.
A semiconductor integrated circuit device comprising:
- an inverter including a PMOS transistor and an NMOS transistor;
- an input unit configured to transfer an input signal to gates of the PMOS transistor and the NMOS transistor;
- a first stress application unit electrically coupled between the gate and a drain of the PMOS transistor and configured to apply stress to the PMOS transistor;
- a second stress application unit electrically coupled between the gate and a drain of the NMOS transistor and configured to apply the stress to the NMOS transistor;
- a first output terminal unit withdrawn from an output node of the inverter;
- a second output terminal unit withdrawn from a source node of the PMOS transistor;
- a loop forming unit configured to electrically couple a source node of the NMOS transistor and the second output terminal unit;
- a first switching unit electrically coupled between the drain of the PMOS transistor and an output node of the inverter;
- a second switching unit electrically coupled between the output node of the inverter and the drain of the NMOS transistor;
- a third switching unit located in the second output terminal unit;
- and
- a fourth switching unit located in the loop forming unit.
A method of measuring a degree of degradation in each of a PMOS transistor and an NMOS transistor in an inverter structure including the PMOS transistor, the NMOS transistor, a first switching unit electrically coupled between the drain of the PMOS transistor and an output node of the inverter, a second switching unit electrically coupled between the output node of the inverter and the drain of the NMOS transistor, a third switching unit located in the second output terminal unit;
- and a fourth switching unit located in the loop forming unit, the method comprising:
- measuring an initial first current path flowing through the PMOS transistor in a state in which a current path flowing through the NMOS transistor is blocked;
- applying stress to the PMOS transistor by providing a gate-drain voltage of the PMOS transistor having a negative level;
- checking whether a first current path flowing through the PMOS transistor in which the stress is received is generated when the first and third switching units are turned on and the second and fourth switching units are turned off;
- and
- measuring the degree of degradation in the PMOS transistor through a variation in the first current path.
A semiconductor integrated circuit device comprising:
- first and second transistors driven by a first power voltage or a second power voltage and electrically coupled to be driven as an inverter in stress application;
- and
- a selection cutting circuit unit selectively electrically coupled to the first and second transistors, and configured to allow a degree of degradation to be separately measured in the first and second transistors in a measurement mode,
- wherein the selection cutting circuit unit includes:
- a first switching unit electrically coupled between a drain of the first transistor and a connection node of the first and second transistors;
- a second switching unit electrically coupled between the connection node and a drain of the second transistor;
- a first output terminal unit withdrawn from the connection node;
- a second output terminal unit withdrawn from a source node of the first transistor;
- a loop forming unit configured to electrically couple a source of the second transistor and the second output terminal unit;
- a third switching unit located in the second output terminal unit;
- and
- a fourth switching unit located in the loop forming unit.
Dependencies are inferred from the claim text.