Test method and test arrangement

A test method, comprising:

• providing a workpiece comprising a transistor to be tested, the transistor comprising a plurality of cells electrically connected in parallel, each of the plurality of cells comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is separately controllable from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode;
• and
• applying a plurality of test potentials to at least one of the at least one additional electrodes of the plurality of cells to detect defective cells among the plurality of cells
• wherein respectively for each of the plurality of cells, a potential of the at least one additional electrode is electrically insulated from potentials of each of the at least one first terminal electrode region, the at least one second terminal electrode region, and the at least one gate electrode,
• wherein the first terminal electrode region is a source region and the second terminal electrode region is a drain region or the first terminal electrode region is a drain region and the second terminal electrode region is a source region.