Low gds measurement methodology for MOS
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYung-Chow Peng, Po-Zeng Kang
Life of this patent
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Abstract
A dummy MOSFET is connected in series with a device under test to form cascode structure. The conductance of the low conductance MOSFET is derived from the measurements done on the cascode structure. An open loop gain stage is connected to the cascode structure in case the signal at the internal node of the cascode structure is extremely small to be measured directly and accurately. Impedance measurements can also be done on high impedance MOS devices without noise distortion with the help of the cascode arrangement.
Claims18
A method for measuring the conductance of a low conductance metal oxide semiconductor (MOS), the method comprising:
- forming a cascode structure comprising a first MOS device and a second MOS device connected together in series, an output node, an internal node that couples the first MOS device to the second MOS device, a first gate contact associated with a gate of the first MOS device configured to receive a gate voltage Vg1, and a second gate contact associated with a gate of the second MOS device configured to receive a gate voltage Vg2, the second MOS device comprising a dummy device, wherein the first MOS is connected to an open loop gain stage when a signal at the internal node is smaller than a predetermined low limit value, and wherein the predetermined low limit value identifies a minimum signal reliability threshold;
- measuring a gain of the cascode structure;
- measuring a transconductance (gm) of the first MOS device;
- and
- deriving a conductance (gds) of the first MOS device from the gain of the cascode structure and the transconductance of the first MOS device.
A method of characterizing a high impedance or low conductance metal oxide semiconductor field effect transistor (MOSFET) under test, the method comprising:
- forming a cascode structure by connecting a first MOSFET device and a second MOSFET device together in series the second MOSFET device comprises a dummy device and the cascode structure comprises an output node at one end location of the first MOSFET, an internal node at a middle location of the cascode structure where the first MOSFET couples to the second MOSFET, a first gate contact associated with a gate of the first MOSFET device configured to receive a gate voltage Vg1 and a second gate contact associated with a gate of the second MOSFET device configured to receive a gate voltage Vg2;
- connecting an open gain stage to the first MOSFET device when a signal at the internal node is smaller than a predetermined low limit value, wherein the predetermined low limit value identifies a minimum signal reliability threshold;
- measuring a gain of the cascode structure by dividing a change in a voltage at the output node by a change in a voltage at the internal node;
- measuring a transconductance (gm) of the first MOSFET device, maintaining a voltage at the gate of the first MOSFET device and dividing an output current by a voltage at the output node;
- and
- deriving a conductance of the first MOSFET device by dividing the gain of the cascode structure by the transconductance of the first MOSFET device.
A test control device, comprising:
- a first voltage source attached to a gate of a first MOSFET device;
- a second voltage source attached to a gate of a second MOSFET device;
- a source measure unit (SMU) which is connected to an output node of the first MOSFET device;
- and
- a source measure unit which is connected to an internal node of a cascode structure, wherein the first MOSFET device is connected to an open loop gain stage when a signal at the internal node is smaller than a predetermined low limit value, and wherein the predetermined low limit value identifies a minimum signal reliability threshold.
Dependencies are inferred from the claim text.