Solder void reduction for component attachment to printed circuit boards

A method comprising:

• fabricating a printed circuit board, wherein the fabricating comprises, forming a first conductive layer on top a first dielectric layer;
• forming a second dielectric layer on top of the at least one first conductive layer;
• forming a second conductive layer on top of the second dielectric layer;
• forming a third dielectric layer on top of the second conductive layer;
• forming a thermal pad on top of the third dielectric layer, wherein an electronic package is to be soldered on top of the thermal pad;
• forming a first through hole through the thermal pad, the third dielectric layer, the second conductive layer, the second dielectric layer, the first conductive layer, and the first dielectric layer;
• filling the first through hole with a conductive material to form a plated through hole;
• and
• topdrilling the plated through hole to remove a top portion of the conductive material from a top of the plated through hole, wherein a bottom portion of the conductive material remains in the plated through hole after removal of the top portion.