Combination HEVC deblocker/SAO filter
AssigneeBroadcom Corporation
InventorTimothy Moore Hellman
Life of this patent
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Abstract
Systems and methods are provided that allow a deblocking filter and a sample adaptive offset (SAO) filter to be combined in a loop filter stage of a High Efficiency Video Coding (HEVC) decoder. In combining the deblocking filter and the SAO filter, an intermediate buffer may not be utilized, while still allowing for the deblocking filter and the SAO filter to operate substantially in parallel. The order of pixel processing and the parallelization of operation is such that the processing performed by the SAO filter need not hinder the processing performed by the deblocking filter within the loop filter stage. Additionally, and by combining the deblocking filter and the SAO filter without utilizing buffering therebetween, savings in space and cost in implementing the HEVC decoder may be realized.
Claims19
A method, comprising:
- in a pipeline processing circuitry comprising a single pipeline stage including a
- combined deblocking filter and sample adaptive offset (SAO) filter;
- receiving, at the combined deblocking filter and SAO filter, at least filter type information indicating a type of filter to be utilized by the deblocking filter and offset information indicating an offset to add to one or more pixels of a first group of pixels at a same stage time from a register buffer;
- deblocking the first group of pixels associated with a first processing block of pixels at a deblocking filter;
- transmitting the deblocked first group of pixels directly without buffering to a sample SAO filter;
- filtering the deblocked first group of pixels at the SAO filter;
- and
- outputting the filtered and deblocked first group of pixels.
A computer program product, stored on a non- transitory computer-readable medium, comprising:
- computer code for receiving at a loop filter stage of pipeline processing circuitry of a video decoder, a reconstructed video signal divided into at least one processing block from a first pipeline stage;
- computer code for reading from a register buffer load information for controlling a combination deblocking and SAO filter at a same stage time, wherein the load information including at least filter type information indicating a type of filter to be utilized by the deblocking filter and offset information indicating an offset to add to one or more pixels of a first group of pixels;
- computer code for performing substantially in parallel, deblocking filtering and sample adaptive offset (SAO) filtering on the processing block, wherein the at least one processing block is provided directly from the deblocking filtering without buffering to the SAO filtering;
- and
- computer code for sending filtered pixels making up the at least one processing block to an output stage.
A system comprising,
- a pipeline processing circuitry comprising a single pipeline stage including a combination deblocking and sample adaptive offset (SAO) filter for deblocking a first group of pixels associated with a first processing block of pixels and adding an offset value to one or more pixels of the first group of pixels, wherein a deblocking filter portion of the combination deblocking and SAO filter passes output data directly without buffering to a SAO filter portion of the combination deblocking and SAO filter;
- a register buffer for holding register load information for controlling the combination deblocking and SAO filter at a same stage time, wherein the load information including at least filter type information indicating a type of filter to be utilized by the deblocking filter and offset information indicating an offset to add to one or more pixels of the first group of pixels;
- and
- at least one pixel buffer for, in conjunction with the register buffer, decoupling the system from additional stages of a video decoder.
Dependencies are inferred from the claim text.