Two-dimensional transformation with minimum buffering
AssigneeAmbarella, Inc.
InventorManish K. Singh
Life of this patent
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AssigneeAmbarella, Inc.
InventorManish K. Singh
Estimating the term…
An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a sequence of intermediate matrices by multiplying a sequence of original matrices by a predetermined matrix and (ii) write the intermediate matrices into a memory in a first order that alternates between (a) a first of the intermediate matrices in a row order and (b) a second of the intermediate matrices in a column order. The second circuit may be configured to (i) read the sequence of the intermediate matrices from the memory in a second order that alternates between (a) the first intermediate matrix in the column order and (b) the second intermediate matrix in the row order and (ii) generate a sequence of transform matrices by multiplying the intermediate matrices as read from the memory by another predetermined matrix.
An apparatus comprising:
A method for transform with minimum buffering, comprising the steps of:
An apparatus comprising:
Dependencies are inferred from the claim text.