Single-lane, twenty-five gigabit ethernet
AssigneeIntel Corporation
InventorsAlain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
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AssigneeIntel Corporation
InventorsAlain Gravel, Robert G. Southworth, Jonathan A. Dama, Ilango S. Ganga, Matthew J. Webb
Estimating the term…
Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.
A network port logic for high-speed data transmission, the network port logic comprising:
A method for high-speed data transmission, the method comprising:
One or more non-transitory computer-readable storage media comprising a plurality of instructions that in response to being executed cause a network port logic to:
Dependencies are inferred from the claim text.