Self track scheme for multi frequency band serializer de-serializer I/O circuits

An apparatus for serializing and de-serializing chip-to-chip communications, comprising:

• a track pulse generator, configured for generating track pulses, within a serializer configured for serializing words of digital data into multiple analog frequency signals for communication to an off chip de-serializer;
• multiple transmitter data buffers configured for receiving digital data bits;
• wherein said multiple transmitter data buffers load data bits in response to receipt of a synchronization signal which is also received at said track pulse generator;
• multiple modulator circuits, each modulator circuit operating at a different modulation frequency;
• said modulator circuits are configured for converting said track pulses and outputs from said multiple transmitter data buffers into an analog signal modulated into carrier signals at multiple frequencies for transmission to a de-serializer;
• multiple demodulator circuits within a de-serializer configured for demodulating and de-serializing data from multiple analog frequency signals received from a serializer, and outputting digital data;
• wherein each demodulator circuit operates at a different modulation frequency;
• and
• wherein said demodulator circuits are configured for converting analog signals modulated into carrier signals at multiple frequencies into words of digital data;
• a track pulse restoration circuit, configured for restoring the track pulse from the transmitter and generating multiple synchronization signals;
• and
• multiple receiver data buffers configured for receiving digital data bits from said demodulator circuits;
• wherein output of digital data from each said demodulator is triggered in response to a first synchronization signal from said track pulse restoration circuit;
• wherein said digital data from each said demodulator is latched into each of said multiple receiver data buffers in response to receipt of a second synchronization signal from said track pulse restoration circuit;
• and
• wherein said digital data is read from said data buffers in response to a third synchronization signal from said track pulse restoration circuit.

A method for serializing and de-serializing chip-to-chip communications, comprising:

• generating track pulses within a serializer of a first device chip;
• storing a digital data word for transmission from the first device chip;
• serializing said track pulses and said digital data word and modulating them into multiple frequency analog signals for communication a de-serializer in a second device chip;
• demodulating the multiple frequency analog signals received at the second device chip;
• performing restoration of the track pulse received from said first device chip;
• and
• controlling the collection of data bits of said digital data word into output buffers in response to synchronization signals timed in relation to restoration of the track pulse.