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US 9,426,004 B1Granted
Method for reducing jitter in receivers
AssigneeMicrosemi Storage Solutions (U.S.), Inc.
InventorWilliam D. Warner
Life of this patent
Estimating the term…
Abstract
A receiver equalizer that provides improved jitter tolerance relative to common adaptation mechanisms and that also provides inter-symbol interference. Improved jitter tolerance is an important benefit for SERDES receivers as tolerance to Sinusoidal Jitter is an important performance metric specified in most industry standards.
Claims15
A method of controlling a receiver equalizer, the method comprising:
- receiving an analog signal having a baud rate;
- sampling the analog signal at a sampling rate of twice that of the baud rate, the sampling to obtain a sampled signal that includes two interleaved digital signals, a first signal of the two interleaved digital signals being a data signal, the data signal comprising data samples sampled at a center of each consecutive symbol of the analog signal, a second signal of the two interleaved digital signals being a timing signal, the timing signal comprising timing samples sampled between consecutive symbols of the analog signal, and the timing samples comprising zero crossing transitions and non-zero crossing transitions;
- identifying the timing samples of the non-zero crossing transitions;
- calculating a timing error term for the timing samples of the non-zero crossing transitions;
- and
- controlling the receiver equalizer as a function of the timing error term.
3 more elements
A receiver comprising:
- a sampler for sampling an analog signal having a baud rate, the sampler to sample the analog signal at a sampling rate of twice that of the baud rate, the sampling to obtain a sampled signal that includes two interleaved digital signals, a first signal of the two interleaved digital signals being a data signal, the data signal comprising data samples sampled at a center of each consecutive symbol of the analog signal, a second signal of the two interleaved digital signals being a timing signal, the timing signal comprising timing samples sampled between consecutive symbols of the analog signal, and the timing samples comprising zero crossing transitions and non-zero crossing transitions;
- a processor operationally connected to the sampler, the processor to identify the timing samples of the non-zero crossing transitions and calculate a timing error term of the timing samples of the non-zero crossing transitions;
- an equalizer to equalize one of the sampled signal and the analog signal;
- and
- a control module operationally connected to the processor and to the equalizer, the control module to control the equalizer as a function of the timing error term.
2 more elements
Dependencies are inferred from the claim text.